UARTConnect enumeration working!
- Fixed cli reflash mode set - Cleaned up debugging code - 4 500 000 baud seems to be reliable - Fixed master selection (assumes slave node unless USB enumerates)
This commit is contained in:
Jacob Alexander
parent
6c67bc77bc
commit
55d03f448e
9 changed files with 261 additions and 137 deletions
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@ -42,8 +42,11 @@ case uartNum: \
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} \
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for ( uint8_t c = 0; c < count; c++ ) \
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{ \
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printHex( buffer[ c ] ); \
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print( " +" #uartNum NL ); \
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if ( Connect_debug ) \
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{ \
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printHex( buffer[ c ] ); \
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print( " +" #uartNum NL ); \
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} \
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uart##uartNum##_buffer[ uart##uartNum##_buffer_tail++ ] = buffer[ c ]; \
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uart##uartNum##_buffer_items++; \
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if ( uart##uartNum##_buffer_tail >= uart_buffer_size ) \
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@ -87,23 +90,35 @@ case uartNum: \
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while ( available-- > 0 ) \
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{ \
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uint8_t byteRead = UART##uartNum##_D; \
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printHex( byteRead ); \
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print( "(" ); \
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printInt8( available ); \
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print( ") <-" ); \
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if ( Connect_debug ) \
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{ \
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printHex( byteRead ); \
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print( "(" ); \
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printInt8( available ); \
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print( ") <-" ); \
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} \
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switch ( uart##uartNum##_rx_status ) \
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{ \
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case UARTStatus_Wait: \
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print(" SYN "); \
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if ( Connect_debug ) \
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{ \
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print(" SYN "); \
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} \
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uart##uartNum##_rx_status = byteRead == 0x16 ? UARTStatus_SYN : UARTStatus_Wait; \
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break; \
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case UARTStatus_SYN: \
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print(" SOH "); \
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if ( Connect_debug ) \
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{ \
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print(" SOH "); \
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} \
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uart##uartNum##_rx_status = byteRead == 0x01 ? UARTStatus_SOH : UARTStatus_Wait; \
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break; \
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case UARTStatus_SOH: \
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{ \
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print(" CMD "); \
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if ( Connect_debug ) \
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{ \
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print(" CMD "); \
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} \
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uint8_t byte = byteRead; \
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if ( byte <= Animation ) \
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{ \
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@ -122,14 +137,20 @@ case uartNum: \
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uart##uartNum##_rx_status = UARTStatus_Wait; \
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break; \
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default: \
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print("###"); \
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if ( Connect_debug ) \
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{ \
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print("###"); \
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} \
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break; \
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} \
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break; \
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} \
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case UARTStatus_Command: \
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{ \
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print(" CMD "); \
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if ( Connect_debug ) \
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{ \
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print(" CMD "); \
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} \
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uint8_t (*rcvFunc)(uint8_t, uint16_t(*), uint8_t) = (uint8_t(*)(uint8_t, uint16_t(*), uint8_t))(Connect_receiveFunctions[ uart##uartNum##_rx_command ]); \
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if ( rcvFunc( byteRead, (uint16_t*)&uart##uartNum##_rx_bytes_waiting, uartNum ) ) \
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uart##uartNum##_rx_status = UARTStatus_Wait; \
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@ -141,7 +162,10 @@ case uartNum: \
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available++; \
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continue; \
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} \
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print( NL ); \
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if ( Connect_debug ) \
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{ \
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print( NL ); \
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} \
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} \
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}
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@ -193,6 +217,11 @@ uint8_t Connect_id = 255; // Invalid, unset
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uint8_t Connect_master = 0;
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// -- Control Variables --
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uint32_t Connect_lastCheck = 0; // Cable Check scheduler
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uint8_t Connect_debug = 0; // Set 1 for debug
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// -- Rx Status Variables --
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volatile UARTStatus uart0_rx_status;
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@ -398,12 +427,16 @@ uint8_t Connect_receive_CableCheck( uint8_t byte, uint16_t *pending_bytes, uint8
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// Check if this is the first byte
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if ( *pending_bytes == 0xFFFF )
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{
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dbug_msg("PENDING SET -> ");
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printHex( byte );
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print(" ");
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*pending_bytes = byte;
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printHex( *pending_bytes );
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print( NL );
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if ( Connect_debug )
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{
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dbug_msg("PENDING SET -> ");
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printHex( byte );
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print(" ");
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printHex( *pending_bytes );
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print( NL );
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}
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}
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// Verify byte
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else
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@ -448,11 +481,15 @@ uint8_t Connect_receive_CableCheck( uint8_t byte, uint16_t *pending_bytes, uint8
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Connect_cableOkSlave = 1;
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}
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}
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dbug_msg("CABLECHECK RECEIVE - ");
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printHex( byte );
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print(" ");
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printHex( *pending_bytes );
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print(NL);
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if ( Connect_debug )
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{
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dbug_msg("CABLECHECK RECEIVE - ");
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printHex( byte );
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print(" ");
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printHex( *pending_bytes );
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print( NL );
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}
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// Check whether the cable check has finished
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return *pending_bytes == 0 ? 1 : 0;
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@ -462,7 +499,7 @@ uint8_t Connect_receive_IdRequest( uint8_t byte, uint16_t *pending_bytes, uint8_
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{
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dbug_print("IdRequest");
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// Check the directionality
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if ( !to_master )
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if ( to_master )
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{
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erro_print("Invalid IdRequest direction...");
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}
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@ -487,7 +524,7 @@ uint8_t Connect_receive_IdEnumeration( uint8_t id, uint16_t *pending_bytes, uint
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{
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dbug_print("IdEnumeration");
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// Check the directionality
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if ( to_master )
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if ( !to_master )
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{
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erro_print("Invalid IdEnumeration direction...");
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}
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@ -511,7 +548,7 @@ uint8_t Connect_receive_IdReport( uint8_t id, uint16_t *pending_bytes, uint8_t t
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{
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dbug_print("IdReport");
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// Check the directionality
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if ( !to_master )
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if ( to_master )
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{
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erro_print("Invalid IdRequest direction...");
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}
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@ -690,7 +727,10 @@ void Connect_setup( uint8_t master )
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// Register Connect CLI dictionary
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CLI_registerDictionary( uartConnectCLIDict, uartConnectCLIDictName );
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// Check if master
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Connect_master = master;
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if ( Connect_master )
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Connect_id = 0; // 0x00 is always the master Id
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// Master / UART0 setup
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// Slave / UART1 setup
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@ -699,15 +739,10 @@ void Connect_setup( uint8_t master )
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SIM_SCGC4 |= SIM_SCGC4_UART1; // Disable clock gating
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// Pin Setup for UART0 / UART1
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// XXX TODO Set to actual (Teensy 3.1s don't have the correct pins available)
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PORTB_PCR16 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
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PORTB_PCR17 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
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PORTC_PCR3 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
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PORTC_PCR4 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
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//PORTA_PCR1 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); // RX Pin
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//PORTA_PCR2 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); // TX Pin
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//PORTE_PCR0 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
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//PORTE_PCR1 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
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PORTA_PCR1 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); // RX Pin
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PORTA_PCR2 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); // TX Pin
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PORTE_PCR0 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
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PORTE_PCR1 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
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// Baud Rate setting
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UART0_BDH = (uint8_t)(Connect_baud >> 8);
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@ -771,12 +806,44 @@ void Connect_setup( uint8_t master )
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// - SyncEvent is also blocking until sent
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void Connect_scan()
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{
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// Check if Tx Buffers are empty and the Tx Ring buffers have data to send
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// This happens if there was previously nothing to send
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if ( uart0_buffer_items > 0 && UART0_TCFIFO == 0 )
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uart_fillTxFifo( 0 );
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if ( uart1_buffer_items > 0 && UART1_TCFIFO == 0 )
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uart_fillTxFifo( 1 );
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// Check if initially configured as a slave and usb comes up
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// Then reconfigure as a master
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if ( !Connect_master && Output_Available )
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{
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Connect_setup( Output_Available );
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}
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// Limit how often we do cable checks
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uint32_t time_compare = 0x7FF; // Must be all 1's, 0x3FF is valid, 0x4FF is not
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uint32_t current_time = systick_millis_count;
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if ( Connect_lastCheck != current_time
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&& ( current_time & time_compare ) == time_compare
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)
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{
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// Make sure we don't double check if the clock speed is too high
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Connect_lastCheck = current_time;
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// Send a cable check command of 2 bytes
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Connect_send_CableCheck( UARTConnectCableCheckLength_define );
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// If this is a slave, and we don't have an id yeth
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// Don't bother sending if there are cable issues
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if ( !Connect_master && Connect_id == 0xFF && Connect_cableOkMaster )
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{
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Connect_send_IdRequest();
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}
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}
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// Only process commands if uarts have been configured
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if ( uarts_configured )
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{
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// Check if Tx Buffers are empty and the Tx Ring buffers have data to send
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// This happens if there was previously nothing to send
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if ( uart0_buffer_items > 0 && UART0_TCFIFO == 0 )
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uart_fillTxFifo( 0 );
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if ( uart1_buffer_items > 0 && UART1_TCFIFO == 0 )
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uart_fillTxFifo( 1 );
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}
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}
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@ -796,7 +863,7 @@ void cliFunc_connectCmd( char* args )
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switch ( numToInt( &arg1Ptr[0] ) )
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{
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case CableCheck:
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Connect_send_CableCheck( 2 );
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Connect_send_CableCheck( UARTConnectCableCheckLength_define );
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break;
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case IdRequest:
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