Add new PIC::initialize method to clear interrupts after initialization
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18d7dbb927
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2 changed files with 119 additions and 80 deletions
174
src/PIC.cc
174
src/PIC.cc
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@ -59,91 +59,29 @@ PIC::systemPIC()
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* Public
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* Public
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*/
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*/
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void
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PIC::initialize(uint8_t pic1Offset,
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uint8_t pic2Offset,
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uint8_t pic2IRQ)
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{
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initializePICs(pic1Offset, pic2Offset, pic2IRQ);
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// Turn off interrupts.
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kernel::io::outb(PIC1.data, 0xFF);
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kernel::io::outb(PIC2.data, 0xFF);
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}
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void
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void
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PIC::remap(uint8_t pic1Offset,
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PIC::remap(uint8_t pic1Offset,
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uint8_t pic2Offset,
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uint8_t pic2Offset,
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uint8_t pic2IRQ)
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uint8_t pic2IRQ)
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{
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{
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/*
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* Initialization of the PIC chips requires programming both chips together.
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* Each requires a series of four bytes: the first (ICW1) on their command
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* ports, and the subsequent three (ICW2 through ICW4) on their data ports.
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*
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* ICW1 contains the following flags:
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* Bit 0: 1 = ICW4 required, 0 = ICW4 not required
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* Bit 1: 1 = single 8259, 0 = cascading 8259s
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* Bit 2: 1 = 4 byte interrupt vectors, 0 = 8 byte interrupt vectors
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* Bit 3: 1 = level triggered mode, 0 = edge triggered mode
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* Bit 4: 1 = initialization (this is required to be 1 for ICW1)
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* Bits 5, 6, 7 must all be 0
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*
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* ICW2 is the interrupt vector offset that this PIC's interrupt should be
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* mapped to. It must be divisible by 0x8.
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*
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* ICW3 is different for the PIC1 and PIC2. For the PIC1, ICW3 should have
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* one bit set indicating on which IRQ PIC2 (the cascaded PIC) will be. For
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* PIC2, the first three bits of ICW3 indicate on which IRQ it will reside
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* on the PIC1.
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*
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* ICW4 contains the following flags:
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* Bit 0: 1 = 80x86 mode, 0 = MCS 80/85 mode
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* Bit 1: 1 = auto EOI mode, 0 = normal EOI mode
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* Bits 2, 3: PIC2/PIC1 buffering mode
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* Bit 4: 1 = special fully nested mode (SFNM), 0 = sequential mode
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* Bits 5, 6, 7 must all be 0
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*
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* The buffering modes mentioned above are as follows:
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* 00: not buffered
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* 01: not buffered
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* 10: buffered mode PIC2 (PC mode)
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* 11: buffered mode PIC1 (PC mode)
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*
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* See also:
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* http://stanislavs.org/helppc/8259.html
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* http://wiki.osdev.org/PIC
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*/
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// Ensure divisiblity by 8.
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pic1Offset &= ~uint8_t(0x7);
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pic2Offset &= ~uint8_t(0x7);
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// TODO: Implement clamping and error handling.
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uint8_t pic2IRQMask = 0;
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if (pic2IRQ > 0) {
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pic2IRQMask = 1;
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for (int i = 1; i < pic2IRQ; i++) {
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pic2IRQMask <<= 1;
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}
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} else {
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// TODO: We have a problem.
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}
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// Save the current IRQ masks for each PIC
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// Save the current IRQ masks for each PIC
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uint8_t pic1Mask = kernel::io::inb(PIC1.data);
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uint8_t pic1Mask = kernel::io::inb(PIC1.data);
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uint8_t pic2Mask = kernel::io::inb(PIC2.data);
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uint8_t pic2Mask = kernel::io::inb(PIC2.data);
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#ifdef CONFIG_PIC_SHOULD_WAIT
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initializePICs(pic1Offset, pic2Offset, pic2IRQ);
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# define waitIfRequired() io::wait()
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#else
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# define waitIfRequired()
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#endif
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#define sendToPIC(port, byte) \
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kernel::io::outb((port), (byte)); \
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waitIfRequired()
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sendToPIC(PIC1.command, ICW1::Initialize + ICW1::ICW4Required);
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sendToPIC(PIC1.data, pic1Offset);
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sendToPIC(PIC1.data, pic2IRQMask);
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sendToPIC(PIC1.data, ICW4::X86Mode + ICW4::AutoEOI);
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sendToPIC(PIC2.command, ICW1::Initialize + ICW1::ICW4Required);
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sendToPIC(PIC2.data, pic2Offset);
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sendToPIC(PIC2.data, pic2IRQ);
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sendToPIC(PIC2.data, ICW4::X86Mode + ICW4::AutoEOI);
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#undef sendToPIC
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#undef waitIfRequired
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// Restore the saved masks
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// Restore the saved masks
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kernel::io::outb(PIC2.data, pic1Mask);
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kernel::io::outb(PIC2.data, pic1Mask);
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@ -210,4 +148,88 @@ PIC::disableIRQ(uint8_t irq)
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kernel::io::outb(port, value);
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kernel::io::outb(port, value);
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}
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}
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void
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PIC::initializePICs(uint8_t pic1Offset,
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uint8_t pic2Offset,
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uint8_t pic2IRQ)
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{
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/*
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* Initialization of the PIC chips requires programming both chips together.
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* Each requires a series of four bytes: the first (ICW1) on their command
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* ports, and the subsequent three (ICW2 through ICW4) on their data ports.
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*
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* ICW1 contains the following flags:
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* Bit 0: 1 = ICW4 required, 0 = ICW4 not required
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* Bit 1: 1 = single 8259, 0 = cascading 8259s
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* Bit 2: 1 = 4 byte interrupt vectors, 0 = 8 byte interrupt vectors
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* Bit 3: 1 = level triggered mode, 0 = edge triggered mode
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* Bit 4: 1 = initialization (this is required to be 1 for ICW1)
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* Bits 5, 6, 7 must all be 0
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*
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* ICW2 is the interrupt vector offset that this PIC's interrupt should be
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* mapped to. It must be divisible by 0x8.
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*
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* ICW3 is different for the PIC1 and PIC2. For the PIC1, ICW3 should have
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* one bit set indicating on which IRQ PIC2 (the cascaded PIC) will be. For
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* PIC2, the first three bits of ICW3 indicate on which IRQ it will reside
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* on the PIC1.
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*
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* ICW4 contains the following flags:
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* Bit 0: 1 = 80x86 mode, 0 = MCS 80/85 mode
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* Bit 1: 1 = auto EOI mode, 0 = normal EOI mode
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* Bits 2, 3: PIC2/PIC1 buffering mode
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* Bit 4: 1 = special fully nested mode (SFNM), 0 = sequential mode
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* Bits 5, 6, 7 must all be 0
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*
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* The buffering modes mentioned above are as follows:
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* 00: not buffered
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* 01: not buffered
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* 10: buffered mode PIC2 (PC mode)
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* 11: buffered mode PIC1 (PC mode)
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*
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* See also:
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* http://stanislavs.org/helppc/8259.html
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* http://wiki.osdev.org/PIC
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*/
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// Ensure divisiblity by 8.
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pic1Offset &= ~uint8_t(0x7);
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pic2Offset &= ~uint8_t(0x7);
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// TODO: Implement clamping and error handling.
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uint8_t pic2IRQMask = 0;
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if (pic2IRQ < 16) {
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pic2IRQMask = 1;
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for (int i = 1; i < pic2IRQ; i++) {
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pic2IRQMask <<= 1;
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}
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} else {
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// TODO: We have a problem.
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}
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#ifdef CONFIG_PIC_SHOULD_WAIT
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# define waitIfRequired() io::wait()
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#else
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# define waitIfRequired()
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#endif
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#define sendToPIC(port, byte) \
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kernel::io::outb((port), (byte)); \
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waitIfRequired()
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sendToPIC(PIC1.command, ICW1::Initialize + ICW1::ICW4Required);
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sendToPIC(PIC1.data, pic1Offset);
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sendToPIC(PIC1.data, pic2IRQMask);
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sendToPIC(PIC1.data, ICW4::X86Mode);
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sendToPIC(PIC2.command, ICW1::Initialize + ICW1::ICW4Required);
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sendToPIC(PIC2.data, pic2Offset);
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sendToPIC(PIC2.data, pic2IRQ);
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sendToPIC(PIC2.data, ICW4::X86Mode);
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#undef sendToPIC
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#undef waitIfRequired
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}
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} /* namespace x86 */
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} /* namespace x86 */
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25
src/PIC.hh
25
src/PIC.hh
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@ -30,11 +30,26 @@ struct PIC
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static PIC& systemPIC();
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static PIC& systemPIC();
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/**
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/**
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* Initialize and map the PIC chips into the interrupt vector space. The
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* Initialize the PIC chips by mapping their ranges out of the default
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* offsets must be divisible by 8. The `pic2IRQ` argument specifies which
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* (which overlap with the system exceptions). The offsets must be divisable
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* IRQ on first PIC the second PIC will be mapped to.
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* by 8. Once the chips are initialized disable all interrupts.
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*
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* @param [in] pic1Offset Offset of PIC1.
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* @param [in] pic2Offset Offset of PIC2.
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* @param [in] pic2IRQ IRQ on PIC1 where PIC2 will be mapped to.
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*/
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*/
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void remap(uint8_t pic1Offset, uint8_t pic2ffset, uint8_t pic2IRQ);
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void initialize(uint8_t pic1Offset, uint8_t pic2Offset, uint8_t pic2IRQ = 2);
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/**
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* Remap the PIC chips into the interrupt vector space. The offsets must be
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* divisible by 8. The interrupt masks are saved before remapping and
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* restored afterwards.
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*
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* @param [in] pic1Offset Offset of PIC1.
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* @param [in] pic2Offset Offset of PIC2.
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* @param [in] pic2IRQ IRQ on PIC1 where PIC2 will be mapped to.
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*/
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void remap(uint8_t pic1Offset, uint8_t pic2Offset, uint8_t pic2IRQ = 2);
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/**
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/**
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* Notifies the PICs with an End Of Interrupt (EOI) command that the
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* Notifies the PICs with an End Of Interrupt (EOI) command that the
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@ -53,6 +68,8 @@ private:
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uint16_t portForIRQ(uint8_t irq);
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uint16_t portForIRQ(uint8_t irq);
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void enableIRQ(uint8_t irq);
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void enableIRQ(uint8_t irq);
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void disableIRQ(uint8_t irq);
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void disableIRQ(uint8_t irq);
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void initializePICs(uint8_t pic1Offset, uint8_t pic2Offset, uint8_t pic2IRQ);
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};
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};
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} /* namespace x86 */
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} /* namespace x86 */
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